簡介
圖3 .(a) The device structure for two types of JL-GAA and JL-Planar TFTs. (b)-(c) The TEM images of JL-GAA and JL-Planar with 2-nm and 15-nm channel thickness. (d) Transfer ID–VG characteristics of JL-GAA and JL-Planar TFTs. (e) The DIBL of JL-GAA and JL-Planar TFTs.
Y. C. Wu 2013 APPLIED PHYSICS LETTERS
本實驗室也成功研究將Pi型多晶矽閘極穿隧電晶體的結構,應用在電荷捕捉層為SONOS的非揮發性記憶體上(Pi-gate TFET SONOS NVM),此元件的電流導通機制及記憶體讀寫的操作機制都是基於量子穿隧的原理,當施加在1ms17V的脈衝電壓後,此元件的臨界電壓產生4.7 V的劇烈變化,這表示元件寫入的電性非常好。除此之外,我們發現此研究使非揮發性記憶體擁有卓越的元件可靠度。不僅如此,此元件在攝氏85 oC的高溫下靜置10000秒後,損失的儲存電荷只有原本的88%,可推估此元件可耐用十年,仍保有原35%的電荷儲存量。此研究極具學術與產業價值。此論文已發表於2013年的Appl. Phys. Lett. [41]

根據延伸半導體元件微縮之莫爾定律,研究單晶與多晶半導體多層堆疊互補式場效電晶體 (stacked CFET)之前段與後段,高密度三維積體電路應用,並利用三維TCAD模擬進行元件基本物性及電性參數分析,同時預測N1節點的元件特性。與其他子計畫的關係為建立立體三維多層堆疊CFET製程,及其 TCAD 模擬輔助製程參數改良之平台。可以提供整合型計畫中,電路spice程式模擬所需之元件模組參數。此外,為輔助人工智慧及互聯網之大量運算,本子計畫亦將針對低功耗應用,開發具低次臨界擺幅 (SS<60mV/dec)、低操作電壓(VD=0.1V) 、高開關電流比之低功率高效能鐵電場效電晶體(ferroelectric FET)

本研究用3D量子傳輸元件模擬,優化閘極長度為3nm的鰭式電晶體元件,透過固定源極與汲極的摻雜濃度、改變通道的摻雜濃度三種不同模式,比較反轉式 (IM)、累積式 (AC) 以及無接面式 (JL) 模式下的元件特性。模擬結果在三種不同模式下,電晶體的次臨界擺幅約為66mV/dec.DIBL值小於17 mV/V以及臨界電壓約為0.31 V,其中臨界電壓可藉由功函數來做調整。經由模擬整合3nm鰭式電晶體的電特性及電子密度分布,模擬結果顯示在三種不同的模式下,電晶體的在3nm微縮技術節點是可行的。此研究極具學術與產業價值。論文發表於2015 IEEE Electron Device Lett. [56]

1. (a) Device structure and important parameters of simulated 3-nm Gate Length (LG) IM, AC & JL Silicon Bulk FinFET. ID-VG of 3nm Gate length (LG) for N-type and P-type Si Bulk FinFET operating in (b) JL, (d) AC & (f) IM mode respectively; with SS and DIBL values shown inset and ID-VD of 3nm Gate length (LG) for N-type and P-type Si Bulk FinFET operating in (c) JL, (e) AC & (g) IM mode with overdrive voltage (VOV), |VOV| = |VG − VTH|.


Y. C. Wu 2015 IEEE ELECTRON DEVICE LETTERS
本研究用3D元件模擬,透過漂移擴散耦合(coupled drift-diffusion)以及密度梯度(density-gradient)模型,評估並比較閘極長度為1nm3nm,通道材料分別為矽(Si)與鍺(Ge)之超薄無接面式鰭式電晶體應用於6T-SRAM的特性。模擬結果顯示,在超薄主動層的應用中,短通道元件不需要遵循經驗法則TCH=LG/3,閘極長度為1nm元件的開關比值為105;另一方面,Ge UTB-JLFET 6T-SRAM cell具有149 mV的靜態雜訊容限值,其電路特性說明UTB-JLFET可應用於sub-5 nm CMOS技術節點。此研究對於學術與產業具有一定價值。論文發表於2015 IEEE Electron Device Lett. [55]
2. (a) Device structure and important parameters of simulated UTB-JLFET with coupled drift-diffusion (DD) and density-gradient (DG) model. (b) Timing characteristics of the input and output signals of a CMOS inverter for Si UTB-JLFET with LG = 1 nm. (c) Static transfer characteristic curves of Si UTB-JLFET 6T-SRAM cells. The definition of static noise margin (SNM) is the length of the side of the largest square that can be embedded inside the butterfly curve. (d) Timing characteristics of the input and output signals of a CMOS inverter for Ge UTB JLFET with LG = 1 nm. (e) Static transfer characteristic curves of Ge UTB-JLFET 6T-SRAM cells.
Y. C. Wu 2013 Symposia on VLSI Technology and Circuits
本實驗室已經成功發表過2奈米厚的超薄主動層之環繞狀式閘極無接面超薄電晶體,此元件擁有61 mV/dec.的次臨界擺幅值以及108的開關電流比值,此臨界擺幅值是目前發表過有關無接面電晶體的最低記錄。此環狀式閘極無接面電晶體擁有優越的閘極控制能力以及良好的電特性,在LG60奈米不僅擁有非常低的集極電壓造成的能帶降低效應(DIBL=6mV/V),且元件的臨界電壓及次臨界擺幅隨溫度的變化程度也很低。值得一提的是,此元件的製程非常容易,擁有非常大的潛力應用在未來的15奈米以下的互補式金氧半電晶體。此研究極具學術與產業價值。此論文已發表於2013年的Symposia on VLSI Technology and Circuits [1]
Y. C. Wu 2015 IEEE ELECTRON DEVICE LETTERS
Y. C. Wu 2017 APPLIED PHYSICS LETTERS

Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel(0.65 nm) and record sub-threshold slope (43 mV/dec),於世界首先提出  JLFET SS=43 mV/dec,可以突破小於60 mV/dec的紀錄。

圖4 .(a)-(c) Pi-gate TFET SONOS NVM structure. (d) P/E speed and (e) retention of Pi-gate T-SONOS NVM.
圖5. An illustration of the device structure and cross-section of the channel, indicating the A-A0 plane from the source side to the drain side for (a) GAA JLFET and (b) planar JLFET along with the detailed fabrication process flowchart for the GAA JLFET device with ten NWs.
圖6. Cross-sectional TEM images of (a) GAA JLFET (with TCH= 0.65 nm and TOX= 12.3 nm) and (b) planar trench JLFET (with a channel thickness of 10.7 nm in the channel center and 1.68 nm in the channel edge) along BB0 , respectively. (c) and (d) AFM images of GAA JLFET with the gate length of 200 nm. LG= 200 nm, which is defined by the trench length. 
圖7. (a) ID-VG curves of GAA JLFET and planar trench JLFET. The SSavg value is extracted from ID = 2.1 1014 A to ID = 2.1 1011 A. (b) Cumulative distribution of VTH and SS. Each curve is extracted from ten devices. (c) The ID-VG curves of GAA JLFET with the trench structure (SSmin = 43 mV/dec and SSavg = 59 mV/dec) and w/o trench structure (SSmin = 179 mV/dec and SSavg = 206 mV/dec).
Y. C. Wu 2014 IEEE International Electron Device Meeting
於世界首先提出的混合式Hybrid P/N JLFET,使上層的p-type通道,可藉由下層之n-type基板來空乏電洞,因此可以使用較厚的 p-type (24 nm)主動層,不必受限使用小於 10 nm的超薄主動層,也可達到優越的JLFET特性。
於世界首先提出以乾式蝕刻法製作之溝槽式超薄主動層 Si thickness=2.4nm 的 trench JLFET ,並以量子侷限效應,正確計算出臨界電壓的上升。

圖8.  (a) Trench JL-TFT device with ten NWs (b) TEM images of trench JL-TFT with LG=0.3 µm and TCH=4.1 nm. (c) TEM images of trench JL-TFT with LG=0.5 µm and TCH=2.4 nm. The effective channel width (Weff)=[(68 nm+2.4 nm×2)×10]. (d)  Comparison of the ID-VG curves of NWs trench JL-TFT and planar trench JL-TFT devices with LG=0.5 µm.

Y. C. Wu 2014 IEEE International Electron Device Meeting
圖9. (a) Schematic diagram of the proposed hybrid P/N JL-TFT devices with ten NWs. (b) Top view SEM image of the active region of the device with Lg = 1μm. (c) Cross-sectional TEM images of hybrid P/N channel along AA’ direction with omega-gate structure. (d) The enlarged TEM images in Fig. 2(c) with Tch = 24 nm, fin width = 28 nm.
圖10.  (a) Simulated hole density and (b) electrical field distribution in the middle of the channel at off-state (at Vg = -1V) in hybrid P/N channel and single p-channel JL devices with different channel thickness and structure.
圖11.  (a) The transfer Id-Vg characteristics, and (b) DIBL, in hybrid P/N and conventional JL-TFTs with Lg = 1μm at Vd = -0.4V. The hybrid fin channel shows a steep SS of 64mV/dec and a small DIBL value from Lg=1μm to 60nm.

[3-5] B. Obradovic et al., “Ferroelectric Switching Delay as Cause of Negative Capacitance and the Implications to NCFETs,” in Symp. VLSI Technol., Jun. 2018; DOI: 10.1109/VLSIT.2018.8510628

[3-6] Meng-Ju Tsai et al., “Atomic-Level Analysis of Sub-5-nm-Thick Hf0.5Zr0.5O2 and Characterization of Nearly Hysteresis-Free Ferroelectric FinFET,” in IEEE Electron Device Letters, Vol. 40, No. 8, pp. 1233-1236, Aug. 2019; DOI: 10.1109/LED.2019.2922239

[3-7] Chong-Jhe Sun et al., “Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio,” in IEEE Journal of Electron Device Society, vol. 8, pp. 1016-1020, Sep. 2020; DOI: 10.1109/ JEDS.2020.3023953

[3-8] Meng-Ju Tsai et al., “Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors,” in IEEE Electron Device Letters, Vol. 7, pp. 1133-1139, Nov. 2019; DOI: 10.1109/JEDS.2019.2952150

[3-9] Yi-Wen Lin et al., “Self-induced ferroelectric 2-nm-thick Gedoped HfO2 thin film applied to Ge nanowire ferroelectric gate-all-around field-effect transistor,” in Appl. Phys. Lett. 117, 262109 (2020); DOI: 10.1063/5.0029628

[3-10] Vasanthan Thirunavukkarasu et al., “Performance of Inversion, Accumulation, and Junctionless Mode n-Type and p-Type Bulk Silicon FinFETs With 3-nm Gate Length,” in IEEE Electron Device Letters, Vol. 36, Issue. 7, pp. 645-647, May. 2015; DOI: 10.1109/LED.2015.2433303

Reference

近年之研究成果

1. 清大工科吳永俊實驗室於20196月發表,為世界上首先做出 2nm3nm5nmHf0.5Zr0.5O2 鐵電鰭式電晶體(Ferroelectric FinFET),並以原子尺度解析的方式分析鐵電層[3-5]。此研究的重要性是將鐵電 Hf0.5Zr0.5O2 材料製作於鰭式電晶體上,次臨界擺幅(SS)小於波茲曼物理極限 60mV/dec,有超低功耗次世代奈米元件之應用,並與現今矽基半導體元件製程相容,極具量產的可能性。此論文不僅於材料方面的分析,更是實現高性能電晶體特性。發表半年就達到近千次下載及點閱,直到201912月美國柏克萊團隊才參照我們利用同步輻射分析Hf0.5Zr0.5O2 材料薄膜結晶的方法做類似的研究。

3-6: 吳永俊實驗室發表之 (a) & (b) FinFET TEMEDS元素分布圖,(c)2奈米鐵電HZO閘極氧化層TEM圖,(d)HZO閘極氧化層之TEM NBD圖, (e)3 nm HZO 閘極氧化層FinFET電流特性[3-6]

2. 吳永俊實驗室於2020IEEE EDL 發表高載子遷移率 SiGe 通道超薄主動層 N-type FinFET,通道寬度僅5 nm,具超高高寬比接近10倍,其電性具有高開關電流比及低漏電特性,為N3 FinFET製程節點微縮的延續[3-7]

3-7: 吳永俊實驗室發表之(a)高寬比近10倍之SiGe FinFET 通道之EDS元素分布圖,(b)SiGe通道之HRTEM圖,顯示通道寬度僅5nm(b)高通道高寬比SiGe FinFET之電流特性 [3-7]

3. 吳永俊實驗室於2019年,首先製作出多層堆疊奈米薄片全環繞式閘極電晶體,適用於未來3奈米以下節點半導體元件技術以及三維堆疊的元件[3-8]

3-8: 吳永俊實驗室發表之 (a) & (b) 多層堆疊奈米薄片全環繞式閘極電晶體之TEMSTEM暗場圖,(c) 電特性圖,(d) TCAD 電子濃度模擬圖[3-8]

4. 202012月於 APL 發表世界上首次利用Ge自發性摻雜入HfO2形成鐵電閘極氧化層(Ge:HfO2)並以其製成鐵電奈米線閘極環繞式電晶體[3-9],符合未來N2節點所需之GAA結構,不須額外製程步驟便可具有鐵電電晶體之超低功耗特性,提供未來低功耗電晶體一項製程可行的量產方法。

3-9: 吳永俊實驗室發表之 (a-c)為鐵電奈米線閘極環繞式電晶體之通道剖面TEMHRTEMEDS元素分布圖,(d) Ge:HfO2鐵電奈米線閘極環繞式電晶體之電流特性[3-9]

3-10: 吳永俊實驗室發表3nm節點 (a) 3D TCAD FinFET結構模擬之參數,(b)無接面式(Junctionless) FinFET之電性模擬 (f) 反轉式(Inversion mode) FinFET之電性模擬 [3-10]

奈米綠能電子元件實驗室             國立清華大學 工程與系統科學系

Nanoelectronic X-FET Green Devices Labortory       National Tsing Hya University, Department of Engineering and System Science

奈米元件之量子效應


先進非揮發性記憶體


先進太陽能電池

先進奈米電子元件模擬與模型

先進奈米電子元件

其他研究方向